/*
Title: Bus Activity Monitor to Uart Interface
Author: Rajas Mokashi
Created for: ECE510: System Verilog Final Project
Description: This is a interface used between 
             Bus Activity Monitor and the Uart Port(module).
*/

interface BAMToUARTInterface();

  logic [7:0] TransmitData;     // 8 bit data (Control word(CW) if ControlOrData is high)
  logic TransmitDataSent;       // Indicates there is data/CW available on Transmitdata lines
  logic TransmitAcknowledge;    // Used to assert that data has been latched
  logic [7:0] RecieveData;      // 8 bit of recieved data
  logic RecieveDataSent;        // Indicates there is data available on Recievedata lines
  logic RecieveAcknowledge;     // Used to assert that Recieved data has been latched
  logic ControlOrData;          // If high, CW on data lines else Data to be sent
  
  //BAM Output port
  modport BAMToUART(input   TransmitAcknowledge,       // Modport for BAM
                    input   RecieveData,
                    input   RecieveDataSent,
                    output  TransmitData,
                    output  TransmitDataSent,
                    output  RecieveAcknowledge,
                    output  ControlOrData);
                      
  //Uart input port
  modport UARTToBAM(output  TransmitAcknowledge,       // Modport for UART
                    output  RecieveData,
                    output  RecieveDataSent,
                    input   TransmitData,
                    input   TransmitDataSent,
                    input   RecieveAcknowledge,
                    input   ControlOrData);
endinterface
